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19-2062; Rev 0; 5/01
2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust
General Description
The MAX3877/MAX3878 are compact, low-power clock recovery and data retiming ICs for 2.488Gbps SONET/ SDH applications. The fully integrated phase-locked loop (PLL) recovers a synchronous clock signal from the serial NRZ data input, which is retimed by the recovered clock. An additional 2.488Gbps serial input is available for system loopback diagnostic testing, or this input can be connected to a 155MHz reference clock to maintain a valid clock output in the absence of data transitions. The MAX3877/MAX3878 provide vertical threshold and phase-adjust control to optimize system BER in DWDM applications. These devices provide both loss-of-lock (LOL) and loss-of-signal (LOS) monitors. Differential CML outputs are provided for both clock and data signals on the MAX3877, and differential PECL outputs are provided for clock and data signals on the MAX3878. The MAX3877/MAX3878 are designed for both sectionregenerator and terminal-receiver applications in OC48/STM-16 transmission systems. Their jitter performance exceeds all of the SONET/SDH specifications. These devices operate from a single +3.0V to +3.6V supply over a -40C to +85C temperature range. Typical power consumption is only 540mW with a +3.3V supply (MAX3878). They are available in a 32-pin TQFP-EP package with an exposed pad, as well as in die form.
Features
o Exceeds ANSI, ITU, and Bellcore SONET/SDH Specifications o Adjustable Input Threshold (180mV) o 10mVp-p to 1.2Vp-p Differential Input Range o 540mW Power Dissipation (at +3.3V) o Fully Integrated Clock Recovery and Data Retiming o Optional Holdover Capability (Using External Reference Clock) o 0.003UIRMS Clock Jitter Generation o Tolerates >2000 Consecutive Identical Digits o Additional 2.488Gbps Input for Diagnostic Loopback Testing o Differential PECL or CML Data and Clock Outputs o Loss-of-Signal Indicator o Loss-of-Lock Indicator
MAX3877/MAX3878
Ordering Information
PART MAX3877EHJ MAX3877E/D*** MAX3878EHJ MAX3878E/D*** TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 32 TQFP-EP* DICE** 32 TQFP-EP* DICE**
Applications
Long Haul and Metro Systems with Optical Amplification DWDM Transmission Systems SONET/SDH Receivers and Regenerators Add/Drop Multiplexers Digital Cross-Connects SONET/SDH Test Equipment
* Exposed pad ** Dice are designed to operate over this range, but are tested and guaranteed at TA = +25C only. contact factory for availability. *** Future product--contact factory for availability.
Pin Configuration
CPWD+ CPWD-
TOP VIEW
PHADJ
GND
FIL+
LOS 26
32 GND THADJ VCC SDISDI+ VCC SIS LREF 1 2 3 4 5 6 7 8 9 GND
31
30
29
28
27
LOL 25 24 VCC 23 SDO+ 22 SDO21 VCC 20 VCC 19 SCLKO+ 18 SCLKO17 VCC 16 GND
MAX3877 MAX3878
FIL-
10 GND
11 VCC
12 SLBI-
13 SLBI+
14 VCC
15 VCC
Typical Operating Circuit appears at end of data sheet.
TQFP
________________________________________________________________ Maxim Integrated Products
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2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust MAX3877/MAX3878
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC..............................................-0.5V to +5.5V Input Voltage Levels (SDI+, SDI-, SLBI+, SLBI-) ..........(VCC - 0.8V) to (VCC + 0.5V) Input Current Levels (SDI+, SDI-, SLBI+, SLBI-)............................-16mA to +10mA PECL Output Current Levels (SDO+, SDO-, SCLKO+, SCLKO-) .....................0mA to 56mA CML Output Current Level (SDO+, SDO-, SCLKO+, SCLKO-) ...............................22mA Current into LOS, LOL .....................................-600A to +4mA Voltage at LOS, SIS, PHADJ, THADJ, CPWD+, CPWD-, LOL, FIL+, FIL-, LREF.............................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85C) 32-Pin TQFP-EP (derate 22.2mW/C above +85C) ..1444mW Operating Temperature Range MAX3877/MAX3878EHJ ..................................-40C to +85C Operating Junction Temperature Range (die) ..-55C to +150C Storage Temperature Range .............................-65C to +150C Processing Temperature (die) .........................................+400C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25C.) (Note 1)
PARAMETER SUPPLY CURRENT MAX3877 (Note 2) Supply Current INPUT SPECIFICATION (SDI, SLBI) Differential Input Voltage (SDI) Differential System Loopback Input Voltage Range (SLBI) Single-Ended Input Voltage (SDI, SLBI) Input Termination to VCC (SDI, SLBI) VID VID VIS RIN Figure 1 (Note 3) 10 50 VCC 0.6 52 1200 1200 VCC + 0.3 mVp-p mVp-p V ICC MAX3878 (Note 2) 163 250 175 262 mA SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX3878 PECL OUTPUT SPECIFICATION (SDO, SCLKO) PECL Output High Voltage (SDO, SCLKO) TA = 0C to +85C TA = -40C TA = 0C to +85C TA = -40C VCC 1.025 VCC 1.085 VCC 1.81 VCC 1.83 VCC 0.88 VCC 0.88 VCC 1.62 VCC 1.556
V
PECL Output Low Voltage (SDO, SCLKO)
V
MAX3877 CML OUTPUT SPECIFICATION (SDO, SCLKO) CML Differential Output Swing CML Differential Output Impedance CML Output Common-Mode Voltage RO DC-coupling (RL = 50 to VCC) RL = 50 to VCC 640 85 800 100 VCC 0.2 1000 115 mVp-p V
2
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2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX3877/MAX3878
THRESHOLD SETTING SPECIFICATION (SDI) Differential Input Voltage Range Input Threshold Adjustment Range THADJ Voltage Range Threshold Control Linearity Threshold Setting Accuracy Figure 2 VTH = 30mV to 80mV (Note 5, Figure 2) Threshold Setting Stability VTH = 80mV to 180mV (Note 5, Figure 2) Maximum Input Current (THADJ, PHADJ) Control voltage = 0.2V to 2.2V -11.5 -10 +11.5 +10 A VID VTH VTHADJ Note 4 Figure 2 Figure 2 100 -180 0.2 -5 -27 -7.0 600 180 2.2 +5 +27 +7.0 mV mVp-p mV V % mV
TTL INPUT/OUTPUT SPECIFICATION (SIS, LREF, LOL, LOS) TTL Input High Voltage (SIS, LREF) TTL Input Low Voltage (SIS, LREF) TTL Input Current (SIS, LREF) TTL Output High Voltage (LOL>, LOS) TTL Output Low Voltage (LOL>, LOS) VOH VOL IOH = +40A IOL = -2mA VIH VIL -10 2.4 0.4 2.0 0.8 +10 V V A V V
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25C.) (Note 6)
PARAMETER Serial Output Clock Rate Clock-to-Q Delay Jitter Peaking Jitter Transfer Bandwidth JP JBW (Figure 4) f 2MHz 1.1 110 SYMBOL CONDITIONS MIN TYP 2.488 290 0.1 2.0 MAX UNITS Gbps ps dB MHz
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2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust MAX3877/MAX3878
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25C.) (Note 6)
PARAMETER SYMBOL f = 70kHz f = 100kHz (see "Jitter Tolerance" graph in Typical Operating Characteristics) f = 1MHz f = 10MHz Jitter Generation Clock Output Edge Speed Data Output Edge Speed Tolerated Consecutive Identical Digits Input Return Loss (SDI, SLBI) 2.5GHz to 4.0GHz PLL Acquisition Time LOS Assert Time LOS Deassert Time Low-Frequency Cutoff for DC-Cancellation Loop HOLDOVER SPECIFICATION VCO Frequency Drift Rate in the Absence of Data PHASE ADJUST SPECIFICATION Minimum Phase Adjust Range Phase Adjust Stability (Note 7) (Note 8) -60 -8 +60 +8 ps ps df/dt CFIL = 1F 6.2 kHz/s CPWD = 0.1F 14.5 14 1.65 4.0 10 ms s s kHz JGEN Jitter bandwidth = 12kHz to 20MHz 0.026 (20% to 80%) (20% to 80%) BER 10-10 100kHz to 2.5GHz 2000 17 dB 0.056 120 120 UIp-p ps ps bits 0.41 0.36 CONDITIONS MIN TYP 3.18 2.75 UIp-p 0.67 0.45 0.003 0.006 UIRMS MAX UNITS
Jitter Tolerance
Note 1: At TA = -40C, DC characteristics are guaranteed by design and characterization. Note 2: Excluding PECL output termination, CML outputs open. Note 3: Jitter specifications are guaranteed for this data input voltage range, measured by connecting THADJ to VCC. Guaranteed by design and characterization. Note 4: Jitter specifications are guaranteed when input threshold is set to 30% of the differential input swing. Measured with edge speed 150ps (Figure 3). Guaranteed by design and characterization. Note 5: Threshold setting stability is guaranteed by design and characterization. Note 6: AC characteristics are guaranteed by design and characterization. Note 7: Phase adjust is disabled when PHADJ is connected to VCC. Note 8: Phase adjust stability is guaranteed over temperature and power-supply variation.
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2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust MAX3877/MAX3878
SDI+ SDI5mV MIN 600mV MAX
(SDI+) (SDI-)
VID
10mVp-p MIN 1200mVp-p MAX
Figure 1. Input Amplitude
VTH (mV)
+207 +180 -153 THRESHOLD SETTING ACCURACY (PART-TO-PART VARIATION OVER PROCESS)
1.1 0.2 1.3 2.2
THADJ (V)
-153 -180 -207
THRESHOLD SETTING STABILITY (OVER TEMPERATURE OR SUPPLY)
Figure 2. Setting the Input Threshold Level
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2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust MAX3877/MAX3878
(SDI+) - (SDI-) (mV)
+300 (100%) +180
0 (50%) VTH RANGE -180 -300 (0%) VTH STABILITY
Figure 3. Definition of Input Threshold
tCLK (SCLKO+) - (SCLKO-)
tCLK-Q (SDO+)-(SDO-)
Figure 4. Output Clock-to-Q Delay
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
RECOVERED DATA AND CLOCK (DIFFERENTIAL OUTPUT)
MAX3877 toc01
RECOVERED CLOCK JITTER
PRBS = 223 - 1
MAX3877 toc02
JITTER TOLERANCE
MAX3877 toc03
10
INPUT JITTER (UIp-p) CLOCK RMS = 1.33ps
PRBS = 223 - 1 PATTERN VIN = 10mVP-P
TA = +85C
DATA
1
BELLCORE MASK
0.1 100ps/div 10ps/div 10 100 1000 10,000 JITTER FREQUENCY (kHz)
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2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust MAX3877/MAX3878
Typical Operating Characteristics (continued)
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
JITTER TOLERANCE vs. INPUT AMPLITUDE
MAX3877 toc04
JITTER TRANSFER
MAX3877 toc05
BIT ERROR RATIO vs. INPUT AMPLITUDE
MAX3877 toc06
1.0 0.9 JITTER TOLERANCE (UIp-p) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1 10 100 1000 PRBS = 223 - 1 JITTER FREQUENCY = 5MHz JITTER FREQUENCY = 1MHz
0.3 0 -0.3 JITTER TRANSFER (dB) -0.6 -0.9 -1.2 -1.5 -1.8 -2.1 -2.4 -2.7 -3.0 PRBS = 223 - 1 10k 100k 1M BELLCORE MASK
10-3 10-4 BIT ERROR RATIO 10-5 10-6 10-7 10-8 10-9 10-10
PRBS = 223 - 1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
10,000
10M
DIFFERENTIAL INPUT VOLTAGE (mVp-p)
JITTER FREQUENCY (Hz)
DIFFERENTIAL INPUT AMPLITUDE (mVp-p)
SUPPLY CURRENT vs. TEMPERATURE
280 260 SUPPLY CURRENT (mA) 240 220 200 180 160 140 120 100 -50 -25 0 25 50 75 100 AMBIENT TEMPERATURE (C) MAX3878 (EXCLUDING PECL OUTPUT CURRENT) SINUSOIDAL JITTER TOLERANCE (Ulp-p) MAX3877
MAX3877 toc07
JITTER TOLERANCE vs. PULSE-WIDTH DISTORTION
MAX3877 toc08
JITTER TOLERANCE vs. THRESHOLD ADJUST
SINUSOIDAL JITTER TOLERANCE (Ulp-p) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 20 INPUT DATA FILTERED BY 1870MHz 4TH-ORDER BESSEL FILTER PRBS = 223 - 1 30 40 50 60 70 80 fJITTER = 10MHz
MAX3877 toc09
300
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -30 -20 -10 0 10 20 INPUT DATA FILTERED BY 1870MHz 4TH-ORDER BESSEL FILTER fJITTER = 10MHz fJITTER = 5MHz
0.8
PRBS = 223 - 1 INPUT = 300Vp-p 30
INPUT PULSE-WIDTH DISTORTION (%)
INPUT THRESHOLD (% AMPLITUDE)
JITTER TOLERANCE vs. PHASE ADJUST
MAX3877 toc10
JITTER TOLERANCE vs. INPUT PATTERN-DEPENDENT JITTER
SINUSOIDAL JITTER TOLERANCE (Ulp-p) 0.7 0.6 0.5 0.4 0.3 0.2 5 0.1 0 0 PRBS = 223 - 1 0 10 20 30 40 50 60 70 80 fJITTER = 10MHz fJITTER = 5MHz
MAX3877 toc11
TYPICAL DISTRIBUTION OF 100kHz JITTER TOLERANCE
MAX3877 toc12
0.8 SINUSOIDAL JITTER TOLERANCE (Ulp-p) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 PRBS = 223 - 1 0 fJITTER = 10MHz fJITTER = 5MHz
0.8
25
20 PERCENT OF UNITS (%)
15
10
0 -100 -80 -60 -40 -20
20 40 60 80 100
1.90 1.99 2.08 2.17 2.26 2.35 2.44 2.53 2.62 2.71 100kHz JITTER TOLERANCE (UIp-p)
PHASE ADJUST (ps)
PATTERN-DEPENDENT JITTER (ps)
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2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust MAX3877/MAX3878
Pin Description
PIN 1, 9, 10,16, 30 3, 6, 11, 14, 15, 17, 20, 21, 24 2 4 5 7 8 12 13 18 19 22 23 25 26 27 28 29 31 32 NAME GND Supply Ground FUNCTION
VCC
Supply Voltage Threshold Control Voltage Input. Used for setting the data decision threshold. Connect to VCC if not used. See Figure 7. Negative Data Input. 2.488Gbps serial data stream. Positive Data Input. 2.488Gbps serial data stream. Signal Input Selection, TTL. High for system loopback input. See Table 1. Lock to Reference Clock Control Signal, TTL. Negative System Loopback or Reference Clock (in holdover mode) Input Positive System Loopback or Reference Clock (in holdover mode) Input Negative Clock Output, CML (MAX3877) or PECL (MAX3878) Positive Clock Output, CML (MAX3877) or PECL (MAX3878) Negative Data Output, CML (MAX3877) or PECL (MAX3878) Positive Data Output, CML (MAX3877) or PECL (MAX3878) Loss-of-Lock Indicator, TTL Active-Low Loss-of-Signal Indicator, TTL Active-High. LOS is asserted high if there are no incoming data transitions for approximately 1.65s. Phase-Adjust Input. Used to optimize sampling point. Connect to VCC if not used. See Figure 6. Negative PLL Loop Filter Connection. Connect a 1.0F capacitor between FIL+ and FIL-. Positive PLL Loop Filter Connection. Connect a 1.0F capacitor between FIL+ and FIL-. Negative Pulse-Width Distortion Cancellation Capacitor. Connect a 0.1F capacitor between CPWD+ and CPWD-. Positive Pulse-Width Distortion Cancellation Capacitor. Connect a 0.1F capacitor between CPWD+ and CPWD-.
THADJ SDISDI+ SIS LREF SLBISLBI+ SCLKOSCLKO+ SDOSDO+ LOL LOS PHADJ FILFIL+ CPWDCPWD+
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2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust MAX3877/MAX3878
Detailed Description
The MAX3877/MAX3878 consist of a fully integrated phase-locked loop (PLL), input amplifier, data retiming block, and CML output buffer (MAX3877) or PECL output buffer (MAX3878). The PLL consists of a phase/frequency detector (PFD), a loop filter, and a voltage-controlled oscillator (VCO). Figure 5 shows the functional diagram. This device is designed to deliver the best combination of jitter performance and power dissipation by using a fully differential signal architecture and low-noise design techniques. 50mVp-p up to 1200mVp-p. For interfacing with PECL signal levels, see Applications Information.
Phase/Frequency Detector
The phase detector incorporated in the MAX3877 and MAX3878 produces a voltage proportional to the phase difference between the incoming data and the internal clock. Because of its feedback nature, the PLL drives the error voltage to zero, aligning the recovered clock to the center of the incoming data eye for retiming. The digital frequency detector (FD) aids frequency acquisition during startup conditions. The frequency difference between the received data and the VCO clock is derived by sampling the in-phase and quadrature VCO output on the rising edges of the data input signal. The FD drives the VCO until the frequency difference is reduced to zero. Once frequency acquisition is complete, the FD returns to a neutral state. False locking is completely eliminated by this digital frequency detector. While in holdover mode, a Type 4 phase/frequency detector (PFD) is implemented to track the 155MHz reference clock signal. This PFD compares the incoming 155MHz reference clock with the divided down VCO clock. The LREF input is used to enable holdover mode (see Applications Information).
SDI Input Amplifier
The SDI input amplifier accepts 2.488Gbps NRZ data with differential input swing from 10mVp-p up to 1200mVp-p. The bit error rate is better than 1 10-10 for input signals as small as 4mVp-p, though the jitter tolerance performance will be degraded. This amplifier allows for adjustment of the input threshold level. For interfacing with PECL signal levels, see Applications Information, or refer to Applications Note HFAN 1.0, Interfacing Between CML, PECL, and LVDS.
SLBI Input Amplifier
The SLBI input amplifier accepts either 2.488Gbps loopback data or a 155MHz reference clock. This amplifier accepts data with differential input swing from
GND VCC CPWD+ CPWD-
VCC
FIL+
FIL-
THADJ
THRESHOLD ADJUST D Q AMP
SDO+ SDO-
SDIAMP SDI+ 0 MUX 1 AMP SLBI+ SIS LREF LOSS OF SIGNAL DETECTOR LOL LOS DC-OFFSET/ PWD CANCELLATION PHASE & FREQUENCY DETECTOR LOOP FILTER /16 OR /1 VCO AMP SCLKO+ SCLKOPHADJ
SLBI-
LOL LOS
Figure 5. Functional Diagram _______________________________________________________________________________________ 9
2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust MAX3877/MAX3878
PHASE ALIGNMENT vs. PHADJ VOLTAGE
100
DC-Offset/Pulse-Width Distortion Cancellation Loop
The input signal is first limited in the forward signal path. The DC offset of this signal is detected and then amplified in the feedback path. CPWD sets the cutoff frequency of the low pass filter. This error signal is then subtracted from the incoming data. When threshold adjust is enabled, this loop acts as a pulse-width distortion cancellation loop. Shorting the CPWD pins together disables the DC-offset/pulse-width distortion cancellation loop.
PHASE ALIGNMENT (ps)
50
0
-50
Threshold Adjust
0.2 0.7 1.2 PHADJ VOLTAGE 1.7 2.2
-100
Figure 6. Phase Alignment vs. PHADJ Voltage
Phase Adjust
The internal clock is aligned to the center of the data eye. For specific applications, this sampling position can be shifted using the PHADJ input to optimize BER performance. Refer to Figure 6 for setting the voltage at PHADJ. When the phase adjust feature is not used, PHADJ should be tied directly to VCC.
This analog input controls the decision threshold of the input stage. In applications where the noise density is not balanced between logical zeros and ones (i.e., optical amplification using EDFA amplifiers), it is possible to achieve lower bit-error ratios (BER) by adjusting the input threshold. Threshold adjust may be disabled by connecting THADJ to VCC. The threshold level is set relative to the center of the differential input voltage swing at the input. Refer to Figures 3 and 7 for setting the voltage at THADJ.
Input Select Pins
TTL inputs SIS and LREF are provided to select between the SDI and SLBI inputs. Table 1 is a logical truth table describing the operation of SIS and LREF. In this way, the MAX3877/MAX3878 will automatically lock to the reference clock in the event of a loss-of-signal condition. In systems where a valid clock output is required under loss-of-signal conditions, a 155MHz reference clock is applied to the SLBI inputs for holdover capabilities. This holdover mode is activated with the LREF input. LREF may be directly connected to the LOS pin or to an external system loss-of-signal monitor.
THRESHOLD LEVEL vs. VTH VOLTAGE
180
Loop Filter and VCO
The phase detector and frequency detector outputs are summed into the loop filter. An external capacitor, CF, is required to set the PLL damping ratio. Refer to Design Procedure for guidelines on selecting this capacitor. The loop filter output controls the on-chip LC VCO running at 2.488GHz. The VCO provides low phase noise and is trimmed to the correct frequency. Clock jitter generation is typically 1.2psRMS within a jitter bandwidth of 12kHz to 20MHz.
Loss-of-Lock Monitor
A loss-of-lock monitor is incorporated in the MAX3877/MAX3878 frequency detector. When the PLL is frequency locked, the internal LOL signal is high, and if the PLL is out of frequency lock, the internal LOL signal immediately becomes low.
THRESHOLD LEVEL (mV RELATIVE TO 50%)
90
0
Loss-of-Signal Detector
A loss of signal detector is provided to detect a loss of incoming data. If there are no transitions to the SDI data input for approximately 1.65s, the LOS signal becomes high.
-90
-180 0.2 0.7 1.2 THADJ VOLTAGE 1.7 2.2
Figure 7. Threshold Level vs. THADJ Voltage 10 ______________________________________________________________________________________
2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust
Table 1. Selecting Input Path
SIS = 0 LREF = 0 LREF = 1 SDI (Normal Operation) SLBI (Holdover Mode) SIS = 1 SLBI (System Loopback Mode) SLBI (Holdover Mode)
Design Procedure
Setting the Loop Filter
The MAX3877/MAX3878 are designed for both regenerator and receiver applications. The fully integrated PLL is a classic second-order feedback system, with a loop bandwidth (fL) fixed at 1.4MHz. The external capacitor, CF, can be adjusted to set the loop damping. Figures 8 and 9 show the open-loop and closed-loop transfer functions. The PLL zero frequency, fZ, is a function of external capacitor CF, and can be approximated according to:
fZ =
MAX3877/MAX3878
HO(j2f) (dB)
1 2(60)CF
For an overdamped system (fZ / fL < 0.25), the jitter peaking (MP) of a second-order system can be approximated by:
OPEN-LOOP GAIN
CF = 1.0F fZ = 2.6kHz
CF = 0.1F fZ = 26kHz
f MP = 20log 1+ Z fL For example, using CF = 0.1F results in a jitter peaking of 0.16dB. Reducing CF below 0.01F may result in PLL instability. The recommended value of CF = 1.0F is to guarantee a maximum jitter peaking of less than 0.1dB. CF must be a low-TC, high-quality capacitor of type XR7 or better.
f (kHz) 1 10 100 1000
Input Termination
Figure 8. Open-Loop Transfer Function
H(j2f) (dB) CF = 0.1F 0
Inputs for the MAX3877/MAX3878 are current-mode logic (CML) compatible. The inputs all provide internal 50 termination to reduce the required number of external components. When interfacing to differential PECL levels, it is important to attenuate the signal while maintaining a 50 termination (see Figure 10). AC-coupling is also necessary to maintain the input common-mode level.
Output Termination (MAX3877)
CLOSED-LOOP GAIN -3 CF = 1.0F
The MAX3877 uses current-mode logic (CML) for its highspeed digital outputs. CML outputs are 50 back-terminated, reducing the external component count. Refer to Figure 11 for the output structure. CML outputs may be terminated by 50 to VCC, or by 100 differential impedance.
Output Termination (MAX3878)
f (kHz) 1 10 100 1000
Figure 9. Closed-Loop Transfer Function
The MAX3878 uses positive emitter-coupled logic (PECL) for its high-speed outputs. PECL outputs are designed to be terminated by 50 to (VCC - 2V). Refer to Applications Note HFAN 0.1.0, Interfacing Between CML, PECL, and LVDS, for more information.
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2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust MAX3877/MAX3878
VCC
50 0.1F PECL LEVELS 0.1F SDI25
50
The BER is better than 1 10 -10 for input signals greater than 4mVp-p. At 5mVp-p, jitter tolerance will be degraded, but will still be above the SDH/SONET requirement. The user can make a trade-off between jitter tolerance and input sensitivity according to the specific application. Refer to Typical Operating Characteristics for Jitter Tolerance and BER vs. Input Amplitude.
SDI+
Applications Information
Holdover Mode
When in holdover mode, the MAX3877/MAX3878 can lock to an external reference clock to maintain a valid clock output in the absence of input data. When LREF is high, the PLL locks to an external 155.52MHz reference clock, which is applied to the SLBI inputs. To enter holdover mode automatically when there are no transitions to the SDI inputs, LOS can be directly tied to LREF. By maintaining frequency lock, the time required to reacquire lock is reduced.
100
25
MAX3877
System Loopback
Figure 10. Interfacing with PECL Levels
VCC
The system loopback input may be used as an auxiliary input for system loopback testing or as input for an external 155.52MHz reference clock. When used as a loopback test, the user can connect a serializer output in a transceiver directly to the SLBI inputs for system diagnostics. Using an external reference clock can maintain PLL frequency lock in the absence of transitions on the SDI inputs.
50 SDO+ SDO-
50
Consecutive Identical Digits (CID)
The MAX3877/MAX3878 have low frequency drift in the absence of data transitions. As a result, long runs of consecutive zeros and ones can be tolerated while maintaining a BER better than 1 10-10. The CID tolerance is tested using a 213 - 1PRBS, substituting a long run of zeros to simulate the worst case. A CID tolerance of 2000 bits is typical. The VCO frequency after 4096 bits (approximately 1.6s) may be estimated by using the VCO drift rate: 6.2kHz f = 2.488GHz 1.65s x s = 2.488GHz 10.21kHz = 2.488GHz 4.1ppm
MAX3877
Figure 11. CML Outputs
Jitter Tolerance and Input Sensitivity Trade-Offs
When the received data amplitude is higher than 10mVp-p, the MAX3877/MAX3878 provide a typical jitter tolerance of 0.64UI at jitter frequencies greater than 10MHz. The SDH/SONET jitter tolerance specification is 0.15UI, leaving a jitter allowance of 0.49UI for receiver preamplifier and postamplifier design.
Exposed Pad (EP) Package
The exposed pad, 32-pin TQFP incorporates features that provide a very low thermal-resistance path for heat removal from the IC. The pad is electrical ground on the MAX3877/MAX3878 and should be soldered to the circuit board for proper thermal and electrical performance.
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2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust MAX3877/MAX3878
VCC VCC ANALOG INPUTS
VCC OUTIN
VCC SDI-
PHADJ SDO+ SDOCML/PECL
MAX3864 TIA
OUT+ VCC
SDI+ THADJ SLBISLBI+
MAX3877/MAX3878 SCKO+
SCKO-
CML/PECL
LOL LOS SIS LREF
TTL TTL
155MHz
TTL
TTL
Figure 12. Typical Application Circuit (Interfacing with the MAX3864 TIA without using threshold adjust)
Layout Considerations
Performance can be significantly affected by circuit board layout and design. Use good high-frequency design techniques, including minimizing ground inductance and using fixed-impedance transmission lines on the data and clock signals. Power-supply decoupling should be placed as close to VCC as possible. Take care to isolate the input from the output signals to reduce feedthrough.
Chip Information
TRANSISTOR COUNT: 1561 PROCESS: BiPOLAR SUBSTRATE CONNECTED TO GND
______________________________________________________________________________________
13
2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust MAX3877/MAX3878
Typical Application Circuit
VCC VCC GND VCC FIL+ SDIIN TIA AGC SDI+ THADJ SLBISLBI+ PHADJ SIS LREF FIL- CPWD+ CPWDSDO+ SDOCML/PECL 1.0F 1.0F
MAX3877/MAX3878
SCLKO+ SCLKOCML/PECL
LOL LOS
TTL TTL
ANALOG INPUT
155MHz HOLDOVER REFERENCE CLOCK OR 2.5Gbps SYSTEM LOOPBACK DATA
ANALOG INPUT
TTL
TTL
Chip Topography
0.091in 2.311mm CPWD+ CPWDPHADJ GND FIL+ N.C. N.C. LOS FILLOL
N.C. GND GND
GND VCC SDO+
GND SDOTHADJ VCC VCC SDI+ SDIVCC SIS LRE GND VCC SCLKO+ SCLKOVCC GND 0.09in 2.286mm
GND
GND
SLBI-
SLBI+
14
______________________________________________________________________________________
GND
VCC
VCC
N.C.
N.C.
VCC
2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust
Package Information
32L,TQFP.EPS ______________________________________________________________________________________ 15
MAX3877/MAX3878
2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust MAX3877/MAX3878
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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